View ARA2004_5365841.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

04/2011 ARA2004 address-programmable reverse amplifer with step attenuator d ata sheet - r ev 2.2 fea tures ? low cost integrated amplifer with step attenuator ? attenuation range: 0 - 59 db, adjustable in 1 db increments via a 3-wire serial control ? meets docsis distortion requirements at a +60 dbmv output signal level ? low distortion and low noise ? frequency range: 5 - 100 mhz ? 5 volt operation ? -40 to +85 8 c temperature range ? rohs compliant package option applica tions ? mcns/docsis compliant cable modems ? catv interactive set-top box telephony over cable systems ? opencable set-top box ? residential gateway ? product description the ARA2004 is designed to provide the reverse path amplifcation and output level control functions in a catv set-top box or cable modem. it incorporates a digitally controlled precision step attenuator that is preceded by an ultra low noise amplifer stage, and followed by an ultra-linear output driver amplifer. this device uses a balanced circuit design that exceeds the mcns/docsis requirement for harmonic performance s12 package 28-pin ssop with heat slug figure 1: functional block diagram for docsis 3.0 application at a +60 dbmv output level while only requiring a single polarity +5 v supply. both the input and output are matched to 75 ohms with an appropriate transformer. the precision attenuator provides up to 58 db of attenuation in 1 db increments via a three-wire serial interface. with external passive components, this device meets iec 1000-4-12 and ansi/ieee c62.41- 1991 100khz ringwave tests, as well as iec1000-4-5 1.2/50 s surge tests. the ARA2004 is offered in a 28-pin ssop package featuring a heat slug on the bottom of the package. d i p l e x e r a r a 2 0 0 0 s a w f i l t e r d o u b l e - c o n v e r si o n t u n e r m a c u p st r e a m q p s k / 1 6 q a m m o d u l a t o r q a m r e ce i v e r w i t h f e c b a l u n l o w p a ss f i l t e r t r a n s m i t e n a b l e / d i s a b l e e n a b l e d a t a c l o c k a d d r e s s c o n t r o l 2 m i cr o co n t r o l l e r w i t h e t h e r n e t m a c r a m r o m 1 0 b a se - t t r a n sce i v e r r j 4 5 c o n n e c t o r c l o c k c l o c k d a t a d a t a 5 4 - 8 6 0 m h z 4 4 m h z 5 - 4 2 m h z
2 data sheet- rev 2.2 04/2011 ARA2004 figure 2: functional block diagram 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 g n d g n d i s e t 1 a 1 o u t (-) vg 1 a t t i n (-) v c m o s a 1 i n (+ ) a 1 o u t (+ ) c l k a t t i n (+ ) d a t v a t t n en a 1 i n (-) a 2 o u t (-) i s e t 2 a 2 i n (-) vg 2 a t t o u t (-) a 2 o u t (+ ) g n d c m o s a 2 i n (+ ) n / c a t t o u t (+ ) c 1 n / c c 0 figure 3: pin out 3 2 d b 1 6 d b 8 d b 4 d b 2 d b 1 d b e f e t e f e t g a a s i c a t t i n ( + ) a 1 o u t ( + ) a 1 i n ( + ) i s e t 1 v g 1 a 1 o u t ( - ) a 1 i n ( - ) a t t i n ( - ) a t t o u t ( - ) a 2 i n ( - ) a 2 o u t ( - ) v g 2 i s e t 2 a 2 o u t ( + ) a 2 i n ( + ) a t t o u t ( + ) 1 6 d b 1 d b 2 d b 4 d b 8 d b 3 2 d b c m os i c (se r i a l to pa r a l l e l i n te r fa c e ) 8 - b i t s h i f t r e g i st e r / a d d r e ss b u f f e r c o n t r o l l a t ch p 5 p 4 p 3 p 2 p 1 p 0 8 c l o c k d a t a en a b l e
data sheet- rev 2.2 04/2011 ARA2004 3 t able 1: pin description notes: (1) all n/c pins should be grounded. (2) pins should be ac-coupled. no external dc bias should be applied. pin name description pin name description 1 gnd ground 15 n/c no connection (1) 2 v attn supply attenuator 16 n/c no connection (1) 3 att in (+) attenuator (+) input (2) 17 n/c no connection (1) 4 a1 out (+) amplifier a1 (+) output 18 gnd cmos ground for digital cmos circuit 5 a1 in (+) amplifier a1 (+) input (2) 19 att out (-) attenuator (-) output (2) 6 vg1 amplifier a1 (+/-) control 20 a2 in (-) amplifier a2 (-) input (2) 7 i set1 amplifier a1 (+/-) current adjust 21 a2 out (-) amplifier a2 (-) output 8 a1 in (-) amplifier a1 (-) input (2) 22 i set2 amplifier a2 (+/-) current adjust 9 a1 out (-) amplifier a1 (-) output 23 vg2 amplifier a2 (+/-) control 10 att in (-) attenuator (-) input (2) 24 a2 out (+) amplfiier a2 (+) output 11 v cmos supply for digital cmos circuit 25 a2 in (+) amplifier a2 (+) input (2) 12 clk clock 26 att out (+) attenuator (+) output (2) 13 dat data 27 n/c no connection (1) 14 en enable 28 gnd ground
4 data sheet- rev 2.2 04/2011 ARA2004 electrical characteristics t able 2: absolute minimum and maximum ratings t able 3 : operating ranges s tresses in excess of the absolute ratings may cause permanent damage. f unctional operation is not implied under these conditions. e xposure to absolute ratings for extended periods of time may adversely affect reliability. notes: (1) pins 3, 5, 8, 10, 19, 20, 25, 26 should be ac-coupled. no external dc bias should be applied. (2) pins 7 and 22 should be grounded or pulled to ground through a resistor. no external dc bias t he device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defned in the electrical specifcations. parameter min max unit analog supply (pins 2, 4, 9, 21, 24) 0 9 vdc digital supply: v cmos (pin 11) 0 6 vdc amplifier controls: vg1, vg2 (pins 6, 23) -5 2 v rf power at inputs ( pins 5, 8) - +60 dbmv digital interface (pins 12, 13, 14) -0.5 v cmos +0.5 v storage temperature -55 +200 4 c soldering temperature - 260 4 c soldering time - 5 sec parameter min typ max unit amplifier supply: v dd (pins 4, 9, 21, 24) 4.5 5 7 vdc attenuator supply: v attn (pin 2) vdd-0.5 5 7 vdc digital supply: v cmos (pin 11) 3.0 - 5.5 vdc digital interface 0 - vcmos v amplifier controls vg1, vg1 (pins 6, 23) -5 1 2 v case temperature -40 25 85 4 c
data sheet- rev 2.2 04/2011 ARA2004 5 t able 4 : dc electrical specifcations t a = 25 c; v dd , v a ttn , v cmos = +5.0 vdc; vg1, vg2 = +1.0 v (tx enabled) ; v g1, vg2 = 0 v (tx disabled) note: as measured in anadigics test fxture. t able 5a : ac electrical specifcations t a = 25 c; v dd , v a ttn , v cmos = +5.0 vdc; vg1, vg2 = +1.0 v (tx enabled) ; v g1, vg2 = 0 v (tx disabled) parameter min typ max unit comments gain (10 mhz) 27.5 29.3 30.5 db 0 db attenuation setting gain flatness - - 0.75 1.5 - - db 5 to 42 mhz 5 to 65 mhz gain variation over temperature - -0.006 - db/ 4 c attenuation steps: 1 db 2 db 4 db 8 db 16 db 32 db 0.65 1.6 3.6 7.5 15.0 30.2 0.83 1.70 3.75 7.75 15.40 30.75 1.00 2.05 4.0 8.0 15.8 31.3 db monotonic maximum attenuation 58.6 60.3 - db 2 nd harmonic distorion level (10 mhz) - -75 -53 dbc +60 dbmv into 75 ohms 3 rd harmonic distorion level (10 mhz) - -60 -53 dbc +60 dbmv into 75 ohms 3rd order output intercept 78 - - dbmv 1 db gain compression point - 68.5 - dbmv noise figure - 3.0 4.0 db includes input balun loss parameter min typ max unit comments amplifier a1 current (pins 4, 9) - - 48 2.4 80 6 ma tx enabled tx disabled amplifier a2 current (pins 21, 24) - - 77 3.7 120 9 ma tx enabled tx disabled attenuator current (pin 2) - 9 15 ma total power consumption - - 0.67 75 1.08 150 w mw tx enabled tx disabled thermal resistance ( j jc) - 38 - c/w
6 data sheet- rev 2.2 04/2011 ARA2004 t able 5b : ac electrical specifcations (continued) t a = 25 c; v dd , v a ttn , v cmos = +5.0 vdc; vg1, vg2 = +1.0 v (tx enabled) ; v g1, vg2 = 0 v (tx disabled) note: as measured in anadigics test fxture. parameter min typ max unit comments output noise power active / no signal / min. atten. set. active / no signal / max. atten. set. - - - - -38.5 -53.8 dbmv any 160 khz bandwidth from 5 to 42 mhz isolation (45 mhz) in tx disable mode - 65 - db difference in output signal between tx enable and tx disable differential input impedance - 300 - ohms between pins 5 and 8 (tx enabled) input impedance - 75 - ohms with transformer (tx enabled) input return loss (75 ohm characteristic impedance) - - -20 -5 -12 - db tx enabled tx disabled differential output impedance - 300 - ohms between pins 21 and 24 output impedance - 75 - ohms with transformer output return loss (75 ohm characteristic impedance) - - -17 -15 -12 -10 db tx enabled tx disabled output voltage transient tx enable / tx disable - - - 4 100 7 mvp-p 0 db attenuator setting 24 db attenuator setting
data sheet- rev 2.2 04/2011 ARA2004 7 figure 4: t est circuit 2 2 7 1 6 1 5 1 1 4 2 2 2 4 2 5 2 3 2 1 2 0 1 9 1 8 1 7 2 8 2 6 9 8 7 1 0 6 1 1 5 1 2 4 1 3 3 g n d i s e t 1 v g 1 a 1 i n ( + ) a 1 o u t ( + ) a t t i n ( + ) v a t t n v c m o s c l k d a t e n c 0 a 2 o u t ( - ) i s e t 2 a 2 i n ( - ) v g 2 a t t o u t ( - ) g n d c m o s a 2 i n ( + ) a 2 o u t ( + ) n / c n / c c 1 g n d a 1 i n ( - ) a 1 o u t ( - ) a t t i n ( - ) a t t o u t ( + ) ( 7 5 o h m s ) 4 7 0 p f 4 7 0 p f 1 k o h m s 4 7 0 p f 2 k o h m s t u r n s r a t i o 2 : 1 1 5 0 0 p f r f o u t p u t ( 7 5 o h m s ) 0 / + 3 v c o n t r o l a 2 + 5 v 1 u f 0 . 1 u f 3 . 9 o h m s c l o c k e n a b l e d a t a + 5 v 1 0 0 0 p f 1 0 0 0 p f 1 . 2 k o h m s t u r n s r a t i o 1 : 2 r f i n p u t 0 / + 3 v c o n t r o l a 1 + 5 v 1 . 2 k o h m s 1 0 0 0 p f 1 0 0 0 p f 1 u f 0 . 1 u f 1 k o h m s 4 7 0 p f 2 k o h m s a r a 2 0 0 0 1 0 u h 1 0 u h 1 u f 0 . 1 u f + 5 v 1 u f 0 . 1 u f n o t e : p i n s 1 5 a n d 1 6 a r e g r o u n d e d o n t h e a n a d i g i c s t e st f i x t u r e , i d e n t i f y i n g d e v i ce a d d r e ss " 0 0 " . t o k o b a l u n 6 1 6 p t - 1 0 3 0 2 k o h m s 2 k o h m s n o t e : t x e n a b l e : c o n t r o l a 1 a n d c o n t r o l a 2 = + 3 v t x d i s a b l e : c o n t r o l a 1 a n d c o n t r o l a 2 = 0 v
8 data sheet- rev 2.2 04/2011 ARA2004 f igure 5: attenuation level vs c ontrol word 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 control word attenuation (db) figure 6: gain & noise figure vs frequency 5 10 15 20 25 30 35 10 30 50 70 90 frequency (mhz) gain (db) 2 3 4 5 6 7 8 nf (db) gain noise figure figure 7: gain & noise figure vs v dd 20 23 26 29 32 35 3 4 5 6 7 v dd ( volts ) gain (db) 1 2 3 4 5 6 nf (db) ga in noise figure measured @ 30 mhz
data sheet- rev 2.2 04/2011 ARA2004 9 figure 8: gain & noise figure vs t emperature 20 23 26 29 32 35 -40 -25 -10 5 20 35 50 65 80 temperature (c o ) gain (db) 1 2 3 4 5 6 nf (db) ga in noise figure measured @ 30 mhz figure 9: harmonic distortion vs vdd p out = 58 dbmv -80 -70 -60 -50 -40 -30 -20 3 4 5 6 7 v dd ( volts ) harmonic level (dbc) 2nd harmonic 3rd harmonic measured @ 5 mhz figure 10: harmonic distortion vs vdd p out = 58 dbmv -80 -70 -60 -50 -40 -30 -20 3 4 5 6 7 v dd ( volts ) harmonic level (dbc) 2nd harmonic 3rd harmonic measured @ 12 mhz
10 data sheet- rev 2.2 04/2011 ARA2004 f igure 11: harmonic distortion vs t emperature p out = 58 dbmv -80 -75 -70 -65 -60 -55 -50 -45 -40 -40 -25 -10 5 20 35 50 65 80 temperature (c o ) harmonic level (dbc) 2nd harmonic 3rd harmonic measured @ 5 mhz figure 12: harmonic distortion vs power out -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 49 51 53 55 57 59 61 63 65 67 pout (dbmv) harmonics (dbc) 2nd 3rd figure 13: t ransients vs attenuation p out = 55 dbmv at 0 db attenuation ara2000
data sheet- rev 2.2 04/2011 ARA2004 11 -72 -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 -50 0 5 10 15 20 25 30 35 40 frequency (mhz) harmonic level (dbc) 2nd harmonic 3rd harmonic figure 14: harmonic performance over frequency p out =+62 dbmv figure 15: iip2 & iip3 vs frequency 20 24 28 32 36 40 5 15 25 35 45 55 65 75 85 95 frequency (mhz) iip 2 (dbm) 4 6 8 10 12 14 iip 3 (dbm) iip2 iip3 measured @ v dd = 5 volts pin = -20 dbm per tone figure 16: iip2 & iip3 vs vdd 20 24 28 32 36 40 3 4 5 6 7 v dd (volts) iip 2 (dbm) -5 -1 3 7 11 15 iip 3 (dbm) iip2 iip3 measured @ 65 mhz two tones @ 29.5 mhz & 35.5 mhz
12 data sheet- rev 2.2 04/2011 ARA2004 t able 6: programming register logic programming t able 7: data description programming instructions the programming word is set through an 8 bit shift register via the data, clock and enable lines. the data is entered in order with the most signifcant bit (msb) frst and the least signifcant bit (lsb) last. the enable line must be low for the duration of the data entry, then set high to latch the shift register. the rising edge of the clock pulse shifts each data value into the register. software is available from anadigics application engineering to set the data bits through the serial cable on the ARA2004 evaluation board. value function (1 = on, 0 = bypass) p7 n/a p6 n/a p5 32 db atenuator bit p4 16 db attenuator bit p3 8 db attenuator bit p2 4 db attenuator bit p1 2 db attenuator bit p0 1 db attenuator bit data bit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 function p7 p6 p5 p4 p3 p2 p1 p0
data sheet- rev 2.2 04/2011 ARA2004 13 figure 17: serial data input t iming table 8: digital interface specifcation parameter min typ max unit logic high input: v h 2.0 - - v logic low input: v l - - 0.8 v logic input current consumption - - 0.01 ma data to clock set up time: t cs 50 - - ns data to clock hold time: t ch 10 - - ns clock pulse width high: t cwh 50 - - ns clock pulse width low: t cwl 50 - - ns clock to load enable setup ti me : t es 50 - - ns load enable pulse width: t ew 50 - - ns rise time: t r - 10 - ns fall time: t f - 10 - ns d at a c l o c k en abl e en abl e o r d 7 : m sb d 6 d 4 d 3 d 1 d 0 : l sb t cs t ch t cwl t cwh t es t ew
14 data sheet- rev 2.2 04/2011 ARA2004 applica tion informa tion t ransmit enable / disable the ARA2004 includes two amplifcation stages that each can be shut down through external control pins vg1 and vg2 (pins 6 and 23, respectively.) by applying a slightly positive bias of typically +1.0 volts, the amplifer is enabled. in order to disable the amplifer, the control pin needs to be pulled to ground. a practical way to implement the necessary control is to use bias resistor networks similar to those shown in the test circuit schematic (figure 4.) each network includes a resistor shunted to ground that serves as a pull-down to disable the amplifer when no control voltage is applied. when a positive voltage is applied, the network acts as a voltage divider that presents the required +1.0 volts to enable the amplifer. by selecting different resistor values for the voltage divider, the network can accommodate different control voltage inputs. the vg1 and vg2 pins may be connected together directly, and controlled through a single resistor network from a common control voltage. amplifer bias current the i s e t pins (7 and 22) set the bias current for the amplifcation stages. grounding these pins results in the maximum possible current. by placing a resistor from the pin to ground, the current can be reduced. the recommended bias conditions use the confguration shown in the test circuit schematic in figure 4. thermal layout considerations the device package for the ARA2004 features a heat slug on the bottom of the package body. use of the heat slug is an integral part of the device design. soldering this slug to the ground plane of the pc board will ensure the lowest possible thermal resistance for the device, and will result in the longest mtf (mean time to failure.) a pc board layout that optimizes the benefts of the heat slug is shown in figure 18. the via holes located under the body of the device must be plated through to a ground plane layer of metal, in order to provide a suffcient heat sink. the recommended solder mask outline is shown in figure 19. figure 18: pc board layout
data sheet- rev 2.2 04/2011 ARA2004 15 output t ransformer matching the output of the ARA2004 to a 75 ohm load is accomplished using a 2:1 turns ratio transformer. in addition to providing an impedance transformation, this transformer provides the bias to the output amplifer stage via the center tap. the transformer also cancels even mode distortion products and common mode signals, such as the voltage transients that occur while enabling and disabling the amplifers. as a result, care must be taken when selecting the transformer to be used at the output. it must be capable of handling the rf and dc power requirements without saturating the core, and it must have adequate isolation and good phase and amplitude balance. it also must operate over the desired frequency and temperature range for the intended application. esd sensitivity electrostatic discharges can cause permanent damage to this device. electrostatic charges accumulate on test equipment and the human body, and can discharge without detection. although the ARA2004 has some built-in esd protection, proper precautions and handling are strongly recommended. refer to the anadigics application note on esd precautions. figure 19: solder mask outline
16 data sheet- rev 2.2 04/2011 ARA2004 figure 20: s12 package outline - 28 ssop with heat slug
data sheet- rev 2.2 04/2011 ARA2004 17 figure 21: reel dimensions component p ackaging volume quantities for the ara2000 are supplied on tape and reel. each reel holds 3,500 pieces. figure 22: t ape dimensions
18 data sheet- rev 2.2 04/2011 ARA2004 notes
data sheet- rev 2.2 04/2011 ARA2004 19 notes
20 data sheet- rev 2.2 04/2011 ARA2004 notes
war ning anadigics products are not intended for use in life support appliances, devices or systems. use of an anadigics product in any such application without written consent is prohibited. import ant notice anadigics 141 mount bethel road warren, new jersey 07059, u.s.a. tel: +1 (908) 668-5000 fax: +1 (908) 668-5132 url: http://www.anadigics.com anadigics, inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. the product specifcations contained in advanced product information sheets and preliminary data sheets are subject to change prior to a products formal introduction. information in data sheets have been carefully checked and are assumed to be reliable; however, anadigics assumes no responsibilities for inaccuracies. anadigics strongly urges customers to verify that the information they are using is current before placing orders. data sheet - rev 2.2 04/2011 21 ARA2004

▲Up To Search▲

Price & Availability of ARA2004

	To Download ARA2004 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .